This invention relates generally to the transmission and receipt of digitized information, and more particularly relates to an apparatus and method for determining a synchronization signal within an accumulation of received data.
The transmission and receipt of digital data across a communication link has been known in the art for years. In a typical communication system, a transmitter transmits data over a transmission path to a remotely located receiver. The receiver receives the data and passes the data along so that it may be used. As one skilled in the art will readily appreciate, many types of transmitting and receiving equipment may be employed depending upon particular data transmission and receipt requirements.
In modern digital communication systems, data transmission requirements are great. Thus, digital signals are transmitted and received at high frequencies. Thus, equipment at both the transmitting and receiving location must be capable of handling data at the high data transmission rates. In some applications, a single data link is insufficient to obtain large enough data transmission rates. Thus, multiple data links are often employed to obtain the required data transmission rate. As one skilled in the art will readily appreciate, the transmission and receipt of digital data at high frequencies and the associated processing requirements for separating and combining signals requires substantial resources of great complexities.
To somewhat simplify the data transmission and receipt process, standardized protocols have been established. Digital data typically is organized into blocks of digital data, each data block comprising a plurality of bit groups, with the data blocks encoded at the transmitting location and transmitted across the data link. However, data is typically transmitted as a bit stream and it is difficult to relate a particular bit to a corresponding data location. Thus, the transmitter and receiver have been designed to segregate the bit stream into the bit groups. Upon receipt, the bit groups are stored at the receiving location in a sequential manner and represent a sequential bit group in a block of data.
However, when data transmissions are initiated or otherwise interrupted, the receiver does not know which received bit group is the first bit group of a data block and which bit group is the last bit group of the data block. Thus, a synchronization signal is encoded into each data block so that the receiver may determine which bit group is the first bit group in the data block and which bit group represents the last bit group in the data block. Once a synchronization signal is determined, the receiver synchronizes to each subsequently received data block and handles the bit groups accordingly.
In a standard communication protocol, the synchronization signal encoded in a plurality of last bits in various bit groups. For example, in the case of the H.221 communication protocol, each bit group is one byte of data and each data block contains 80 bytes. The synchronization signal is encoded in the eighth bit position of sequentially received bytes of the data block. Thus, by viewing the eighth bit position of a sequentially received number of bytes, the synchronization signal may be determined, and the starting byte and ending byte of each data block may also be determined. Further, because data blocks are transmitted and received sequentially, once a particular starting byte has been determined, the receiver has xe2x80x9clockedxe2x80x9d onto the particular received signal and recognizes each subsequent data block as it is received.
Each data block in a video teleconference may contain audio data, video data, user data, data relating to the control of the other data, time stamp information, and attributes of the equipment at the receiving and transmitting locations. After data is received by the receiver and it is ordered properly, further processing is performed by the receiver so that it can generate the audio, video, and control signals.
In the case of a receiving-transmitting pair that uses a plurality of transmission paths, data blocks may be skewed in time such that they must be reassembled upon receipt. For example, in a system employing five transmission paths with each path sharing a portion of the data transmission workload, data transmitted over respective paths is often skewed in time. In systems employing a plurality of transmissions, once the synchronization signal is determined on each transmission path, the time skewing of the signals may be determined and the timing of the receipt of signals may be determined. Once the synchronization signals are determined for the various transmission paths, the differing blocks of data may more easily be related to one another over time. Time stamps contained in the blocks may be accessed if required and an expeditious reconstruction of the total signal may be accomplished with reduced processing.
One prior art solution for determining the synchronous signal involved using a large shift register having a width of 167 bits. This particular prior art device looked at an ending bit of each byte received by the receiver, shifted the bit into the shift register, and did the same for the remaining 166 ending bits. Decoding circuitry associated with the shift register viewed the 1st through 7th bits, 81st bit, and 161st through 167th bits, and compared the bits with a known synchronization pattern. When a match occurred, the synchronization signal was found and a signal was transmitted from the device to indicate which byte represented the start of the data block. While the particular prior art device accurately determined the synchronous signal, it required significant hardware. Further, in some systems, bits of a transmitted bit group may be transposed due to operation of repeaters along the transmission line. Thus, after transposition, the synchronization signal may reside in an unexpected bit location. The described prior art device could not detect the presence of the synchronization signal in an unexpected bit location. Thus, in some systems the prior art device could not function to determine the synchronization signal.
Another prior art device looked at a single bit of each byte received from the data transmission path and used the bit as an input to a state machine. The state machine, if it received the proper input for seven sequential bits, entered a delay cycle and waited for an 81st bit to compare and check to determine if the bit compared correctly to the expected value. If so, the prior art device issued a synchronization block signal to further components in the system. While this system was inexpensive, it could easily miss the synchronous signal due to falsing, in which case, it would miss a true synchronization signal and would have to wait until the next data block to reinitiate its operation. Further, this prior art device also could not detect the synchronization signal in a bit location other than the expected bit location.
Thus, there exists a need in the art for a highly reliable synchronization signal detect circuit that is efficient in detecting valid blocks, while minimizing the hardware required.